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AMIS-30523 Product Preview CAN Micro-Stepping Motor Driver
Introduction
The AMIS-30523 is a micro-stepping stepper motor driver for bipolar stepper motors with an embedded CAN transceiver. The motor driver is connected through I/O pins and a SPI interface with an external microcontroller. It has an on-chip voltage regulator, reset-output and watchdog reset, able to supply peripheral devices. It contains a current-translation table and takes the next micro-step depending on the clock signal on the "NXT" input pin and the status of the "DIR" (=direction) register or input pin. The CAN transceiver is the interface between a (CAN) protocol controller and the physical bus. It provides differential transmit capability to the bus and differential receive capability to the CAN controller. To cope with the long bus delay the communication speed needs to be low. The integrated transceiver allows low transmit data rates down 10 kbit/s or lower. The AMIS-30523 is ideally suited for general-purpose stepper motor applications in the automotive, industrial, medical, and marine environment. With the on-chip voltage regulator and embedded CAN transceiver it further reduces the BOM for mechatronic stepper applications.
Key Features Motor Driver
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QFN52, 8x8 CASE 485M
MARKING DIAGRAM
1 AMIS30523 0C523-001 XXXXYZZ
* Dual H-Bridge for 2-Phase Stepper Motors * Programmable Peak-Current up to 1.2 A Continuous (1.6 A for a
0C523-001 = Specific Device Code
XXXX = Date Code Short Time)* WL = Wafer Lot * On-Chip Current Translator Y = Assembly Location ZZ = Traceability Code * SPI Interface * Seven Step Modes from Full Step up to 32 Micro-Steps * PWM Current Control with Automatic Selection of Fast and Slow ORDERING INFORMATION Decay and Fully Integrated Current-Sense See detailed ordering and shipping information in the package * Full Output Protection and Diagnosis dimensions section on page 34 of this data sheet. * Thermal Warning and Shutdown * Integrated 5 V Regulator to Supply External * Low EME: Common-Mode Choke is No Longer Microcontroller Required * Differential Receiver with Wide common-mode range CAN Transceiver ($35 V) * Compatible with the ISO 11898 Standard * Voltage Source via VSPLIT Pin for Stabilizing the * Wide Range of Bus Communication Speed (0 up to 1 Recessive Bus Level Mbit/s) * No Disturbance of the Bus Lines with an Un-Powered * Allows Low Transmit Data Rate in Networks Node Exceeding 1 km * Logic Level Inputs Compatible with 3.3 V Devices * Extremely Low Current Standby Mode with Wake-up * These are Pb-Free Devices via the Bus *Output Current Level May be Limited by Ambient Temperature and Heat Sinking
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 2010
November, 2010 - Rev. P0
1
Publication Order Number: AMIS-30523/D
AMIS-30523
BLOCK DIAGRAM
VDD
9 46 Timebase Vreg
CPN CPP VCP
20 40,41 21 22
VBB
25, 26
CLK
Chargepump
CS DI DO NXT DIR SLA POR /WD CLR ERR
24 8 45 10 17 19 42 23 Logic & Registers SPI
POR T R A N S L A T O R
EMC P W M I- sense
38, 39
MOTXP
OTP
34, 35
MOTXN
Load Angle
EMC P W M I- sense
27, 28
MOTYP
Temp. Sense
31,32
MOTYN VCC
4 18
VCC
Band- gap
POR VSPLIT Thermal shutdown
7
TxD
52
VCC
V SPLIT CANH CANL
48
STB
51
Mode & wake -up control
Driver control
49
RxD GND
6 47
Wake-up Filter
COMP
COMP
29,30
36, 37
AMIS-30523
Figure 1. Block Diagram AMIS-30523
GND
1, 2
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AMIS-30523
POR/WD TSTO DO VDD GND CANH CANL
52
51
50
49
48
47
46
45
44
43
42
41
GND GND VCC RxD VSPLIT DI CLK NXT
40
STB TxD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AMIS-30523
VBB VBB
39 38 37 36 35 34 33 32 31 30 29 28 27
MOTXP MOTXP GND GND MOTXN MOTXN MOTYN MOTYN GND GND MOTYP MOTYP
17
18
19
20
21
22
23
24
25
Figure 2. Pin Out AMIS-30523
Table 1. PIN DESCRIPTION
Name GND / VCC / RXD VSPLIT DI CLK NXT / DIR ERRB SLA CPN CPP VCP CLR CSB VBB MOTYP GND Pin 1, 2 3 4 5 6 7 8 9 10 11 .. 16 17 18 19 20 21 22 23 24 25, 26 27, 28 29, 30 Ground No function (to be left open in normal operation) CAN Supply voltage No function (to be left open in normal operation) CAN Receive data output; dominant transmitter low output CAN common-mode stabilization output SPI Data In SPI Clock Input Next micro-step input No function (to be left open in normal operation) Direction input Error output (open drain) Speed load angle output Negative connection of charge pump capacitor Positive connection of charge pump capacitor Charge pump filter-capacitor "Clear" = chip reset input SPI chip select input High voltage supply Input Negative end of phase Y coil output Ground, heat sink Digital Input Digital Output Analog Output High Voltage High Voltage High Voltage Digital Input Digital Input Supply Driver Output Supply Type 1 Type 2 Type 3 Type 2 Type 4 Type 5 Digital Output Supply Digital Input Digital Input Digital Input Type 2 Type 2 Type 2 Supply Description Type Supply Equivalent Schematic
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ERR DIR
CPP CPN SLA
VBB CS CLR VCP
VBB
AMIS-30523
Table 1. PIN DESCRIPTION
Name MOTYN / MOTXN GND MOTXP VBB PORB/WD TST0 / DO VDD GND CANH CANL / STB TXD Pin 31, 32 33 34, 35 36, 37 38, 39 40, 41 42 43 44 45 46 47 48 49 50 51 52 Description Positive end of phase Y coil output No function (to be left open in normal operation) Positive end of phase X coil output Ground, heat sink Negative end of phase X coil output High voltage supply input Power-on-reset and watchdog reset output (open drain) Test pin input (to be tied to ground in normal operation) No function (to be left open in normal operation) SPI data output (open drain) 5V Logic Supply Output (needs external decoupling capacitor) Ground High-level CAN bus line (high in dominant mode) Low-level CAN bus line (low in dominant mode) No function (to be left open in normal operation) CAN stand-by mode control input CAN transmit data input; low input dominant driver; internal pull-up current Digital Input Digital Input Digital Output Supply Supply Analog Output Analog Output Type 4 Type 6 Driver Output Supply Driver Output Supply Digital Output Digital Input Type 3 Type 2 Type Driver Output Equivalent Schematic
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol VBB VCC VCANH, VCANL, VSPLIT VTRANS TST TJ VESD VESD VESD VESD VESD Latch-up Analog DC supply voltage (Note 1) CAN Supply voltage DC voltage CANH ,CANL and VSPLIT (Note 2) Parameter Min -0.3 -0.3 -50 Max +40 +7 +50 Unit V V V
Transient voltage CANH, CANL and VSPLIT (Note 3) Storage temperature Junction Temperature under bias (Note 4) Electrostatic discharges on component level, All pins (Note 5) Electrostatic discharges on component level, All pins (Note 7) Electrostatic discharges on CANH, CANL and VSPLIT (Note 6) Electrostatic discharges on CANH and CANL (Note 7) Electrostatic discharges on component level, HiV pins (Note 6) Static latch-up at all pins
-300 -55 -40 -2 -500 -6 -500 -6
+300 +150 +170 +2 +500 +6 +500 +6 100
V C C kV V kV V kV mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time < 0.5 s. 2. For 0 < VCC < 5.25 V unlimited time 3. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b. 4. Circuit functionality not guaranteed. 5. Standardized Human body model (100 pF via 1.5 kW, according to JEDEC EIA-JESD22-A114-B). 6. Standardized human body model electrostatic discharge (ESD) pulses (100 pF via 1.5 kW) stressed pin to ground. 7. Standardized charged device model ESD pulses when tested according to ESD STM5.3.1-1999.
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Table 3. THERMAL RESISTANCE
Thermal Resistance Junction-to-Exposed Pad (RthJ-EP) 0.95 Junction-to-Ambient (RthJ-A) 1S0P Board 60 2S2P Board 30 Unit K/W
Package QFN-52
EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used.
IN Rpd 4k OUT
TYPE 1: CLR Input
TYPE 4: DO and ERR Open Drain Outputs Rout SLA
IN
4k
TYPE 2: CLK, DI, CS, NXT, DIR Inputs VDD VBB
TYPE 5: SLA Analog Output
VDD
VBB
TYPE 3: VDD and VBB Power Supply
Figure 3. In- and Output Equivalent Diagrams
PACKAGE THERMAL CHARACTERISTICS The AMIS-30523 is available in a QFN-52 package. For cooling optimizations, the QFN has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer. Figure 4 gives an example for good power distribution solutions. For precise thermal cooling calculations the major thermal resistances of the device are given. The thermal media to which the power of the devices has to be given are: * Static environmental air (via the case) * PCB board copper area (via the exposed pad) The thermal resistances are presented in Table 5: DC Parameters Motor Driver. The major thermal resistances of the device are the Rth from the junction to the ambient (RthJ-A) and the overall Rth from the junction to exposed pad (RthJ-EP). In Table 3 one can find the values for the RthJ-A and RthJ-EP, simulated according to JESD-51: The RthJ-A for 2S2P is simulated conform JEDEC JESD-51 as follows: * A 4-layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used * Board thickness is 1.46 mm (FR4 PCB material) * The 2 signal layers: 70 mm thick copper with an area of 5500 mm2 copper and 20% conductivity
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AMIS-30523
an area of 5500 mm2 copper and 90% conductivity The RthJ-A for 1S0P is simulated conform JEDEC JESD-51 as follows: * A 1-layer printed circuit board with a single power and signal layer
* The 2 power internal planes: 36 mm thick copper with
* Board thickness is 1.46 mm (FR4 PCB material) * The layer has a thickness of 70 mm copper with an area
of 5500 mm2 copper and 20% conductivity
Recommend Operation Conditions
Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating
Table 4. OPERATING RANGES
Symbol VBB VCC TJ Motor Driver Analog DC supply CAN transceiver DC supply Junction temperature (Note 8) Parameter
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DO VDD GND CANH CANL
52 51 50 49 48 47 46 45 44 43 42 41
VBB VBB POR/WD TSTO
GND GND VCC
40
STB TxD
1 2 3 4 5 6 7 8 9
39 38 37 36 35 34 33 32 31 30 29 28 27
RxD VSPLIT DI CLK NXT
MOTXP MOTXP GND GND MOTXN MOTXN MOTYN MOTYN GND GND MOTYP MOTYP
10 11
12 13
14
15
16
17
18
19
20
21
22
23
24
25
Figure 4. Example of QFN-52 PCB Ground Plane Layout in Top View (preferred layout at top and bottom)
ELECTRICAL SPECIFICATION ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability.
26
8. No more than 100 cumulative hours in life time above Ttw.
VBB VBB CS CLR VCP CPP CPN SLA ERR DIR
Min 6 4.75 -40
Max 30 5.25 +172
Unit V V C
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Table 5. DC PARAMETERS MOTOR DRIVER
(The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive. Symbol Pin(s) Parameter Remark/ Test Conditions Min Typ Max Unit
SUPPLY AND VOLTAGE REGULATOR VBB IBB IBBS VDD IINT ILOAD IDDLIM ILOAD_PD VDDH VDDL VDDHYS MOTORDRIVER IMDmax,Peak IMdmax,RMS IMdabs IMdrel ISET_TC1 ISET_TC2 RHS RLS3 RLS2 RLS1 RLS0 IMpd Max current through motor coil in normal operation Max RMS current through coil in normal operation Absolute error on coil current Error on current ratio Icoilx / Icoily Temperature coefficient of coil current set-level, CUR[4:0] = 0 ... 27 (Note 10) Temperature coefficient of coil current set-level, CUR[4:0] = 28 ... 31 (Note 10) MOTXP On-resistance high-side driver, MOTXN CUR[4:0] = 0 ... 31 MOTYP MOTYN On-resistance low-side driver, CUR[4:0] = 23 ... 31 On-resistance low-side driver, CUR[4:0] = 16 ... 22 On-resistance low-side driver, CUR[4:0] = 9 ... 15 On-resistance low-side driver, CUR[4:0] = 0 ... 8 Pull down current motor pins -40 C v TJ v 160C -40 C v TJ v 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C VBB = 12 V, TJ = 27C VBB = 12 V, TJ = 160C HiZ mode -10 -7 -240 -490 0.45 0.94 0.45 0.94 0.90 1.9 1.8 3.8 3.6 7.5 1 0.56 1.25 0.56 1.25 1.2 2.5 2.3 5.0 4.5 10 1600 800 10 7 mA mA % % ppm/K ppm/K W W W W W W W W W W mA VDD VDD VBB Nominal operating supply range Total internal current consumption Sleep current in VBB (Note 9) Regulated Output Voltage Internal load current Max. Output Current (external and internal loads) Current limitation Output current in Power Down Unloaded outputs 6 V v VBB < 8 V 8 V v VBB v 30 V Pin shorted to ground 1 15 40 200 Unloaded outputs Unloaded outputs 4.50 5 6 30 8 100 5.50 8 V mA mA V mA mA mA mA mA
POWER ON RESET (POR) Internal POR comparator threshold Internal POR comparator threshold Hysteresis between VDDH and VDDL VDD rising VDD falling 0.1 3.9 4.15 3.80 0.35 0.6 4.4 V V V
9. Characterization Data Only, not tested in production 10. The coil current at a given junction temperature is calculated as: Icoil @ TJ = Icoil [1 + (TJ - 125) x ISET_TCi x 10-6]. See also paragraph Programmable Peak Current. 11. Not valid for pins with internal Pull Down resistor. 12. No more than 100 cumulated hours in life time above Ttw. 13. Thermal shutdown is derived from Thermal Warning.
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Table 5. DC PARAMETERS MOTOR DRIVER
(The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive. Symbol Pin(s) Parameter Remark/ Test Conditions Min Typ Max Unit
DIGITAL INPUTS Ileak VIL VIH Rpd_CLR Rpd_TST VOL DI, CLK Input Leakage (Note 11) NXT, Logic Low Threshold DIR CLR, Logic High Threshold CSB CLR TST0 Internal Pull Down Resistor Internal Pull Down Resistor TJ = 160C 0 2.20 120 3 1 0.65 VDD 300 9 mA V V kW kW
DIGITAL OUTPUTS DO, ERRB, PORB/ WD Logic Low level open drain IOL = 5 mA 0.3 V
THERMAL WARNING & SHUTDOWN Ttw Ttsd CHARGE PUMP VopCP VCP Output voltage 6 V< VBB < 15 V 15 V < VBB < 30 V VBB + 9 2 * VBB -2 VBB + 11.5 VBB + 16 V V Thermal Warning Thermal shutdown (Notes 12 and 13) 138 145 Ttw + 20 152 C C
PACKAGE THERMAL RESISTANCE VALUE RthJ-A QFN package Thermal Resistance Junction-to-Ambient Simulated Conform JEDEC JESD-51, (2S2P) 30 K/W
RthJ-EP
Thermal Resistance Junction-to-Exposed Pad
0.95
K/W
SPEED AND LOAD ANGLE OUTPUT Vout Voff Gsla Rout Cload SLA Output Voltage Range Output Offset SLA pin Gain of SLA Pin = VBEMF / VCOIL Output Resistance SLA pin Load Capacitance SLA pin SLAG = 0 SLAG = 1 (Note 9) (Note 9) 0.2 -50 0.5 0.25 0.23 1 50 kW pF VDD - 0.2 50 V mV
9. Characterization Data Only, not tested in production 10. The coil current at a given junction temperature is calculated as: Icoil @ TJ = Icoil [1 + (TJ - 125) x ISET_TCi x 10-6]. See also paragraph Programmable Peak Current. 11. Not valid for pins with internal Pull Down resistor. 12. No more than 100 cumulated hours in life time above Ttw. 13. Thermal shutdown is derived from Thermal Warning.
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Table 6. AC PARAMETERS MOTOR DRIVER (The AC Parameters are Given for VBB and Temperature in Their Operating Ranges)
Symbol Pin(s) Parameter Remark/ Test Conditions Min Typ Max Unit
INTERNAL OSCILLATOR fosc MOTOR DRIVER fPWM MOTxx fd tbrise MOTxx PWM frequency Double PWM frequency PWM jitter Depth (Note 14) Turn-on voltage slope, 10% to 90% EMC[1:0] = 00 EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 tbfall MOTxx Turn-off voltage slope, 90% to 10% EMC[1:0] = 00 EMC[1:0] = 01 EMC[1:0] = 10 EMC[1:0] = 11 DIGITAL OUTPUTS tH2L DO ERRB Output fall-time from VinH to VinL (Note 14) Capacitive load 400 pF and pull-up resistor of 1.5 kW 50 ns Frequency depends only on internal oscillator 20.8 41.6 22.8 45.6 10 150 100 50 25 150 100 50 25 24.8 49.6 kHz kHz % fPWM V/ms V/ms V/ms V/ms V/ms V/ms V/ms V/ms Frequency of internal oscillator 3.6 4 4.4 MHz
CHARGE PUMP fCP tCPU CPN CPP MOTxx Charge pump frequency Start-up time of charge pump (Note 14) Spec external components See Table 10 250 5 kHz ms
CLR FUNCTION tCLR POWER-UP tPU tPOR tRF WATCHDOG tWDTO tWDPR tNXT_HI tNXT_HI tDIR_SET tDIR_HOLD NXT PORB/ WD Watchdog time out interval Prohibited watchdog acknowledge delay See Figure 23 See Figure 23 32 2 512 ms ms PORB/ WD Power-up time Reset duration Reset filter time VBB = 12 V, ILOAD = 50 mA, CLOAD = 220 nF See Figure 22 See Figure 22 1 110 100 ms ms ms CLR Hard reset duration time 100 ms
NXT FUNCTION NXT Minimum, High Pulse Width NXT Minimum, Low Pulse Width NXT Hold Time, Following Change of DIR NXT Hold Time, Before Change of DIR See Figure 5 See Figure 5 See Figure 5 See Figure 5 2 2 2 2 ms ms ms ms
14. Characterization Data Only, not tested in production.
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tNXT_HI tNXT_LO
NXT
0.5 VCC
tDIR_SET
tDIR_HOLD
DIR
VALID
Figure 5. NXT-Input Timing Diagram
Table 7. SPI TIMING PARAMETERS
Symbol tCLK tCLK_HIGH tCLK_LOW tSET_DI tHOLD_DI tCSB_HIGH tSET_CSB tSET_CLK SPI clock period SPI clock high time SPI clock low time
Parameter
DI set up time, valid data before rising edge of CLK DI hold time, hold data after rising edge of CLK CSB high time CSB set up time, CSB low before rising edge of CLK CLK set up time, CLK low before rising edge of CSB
CS
0.2 VCC tSET_CSB tCLK tSET_CLK
CLK
0.2 VCC tCLK_HI tSET_DI tHOLD_DI tCLK_LO
DI
0.8 VCC VALID
Figure 6. SPI Timing
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IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII
IIIIIIIIII IIIIIIIIII IIIIIIIIII
Min 1 100 100 50 50 2.5 100 100 Typ Max Unit ms ns ns ns ns ms ns ns 0.2 VCC 0.8 VCC 0.2 VCC
III III III II II II II
AMIS-30523
Table 8. DC PARAMETERS CAN TRANSCEIVER
(The DC parameters are given for VCC and temperature in its operating range; TJ = -40 to +150C; RLT = 60 W unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol SUPPLY ICC ICCS ViH ViL IiH IiL Ci ViH ViL IiH IiL Ci VOH VOL Ioh Iol Ci RXD TXD TXD VCC Supply current Supply current in standby mode Dominant; VTxD = 0 V Recessive; VTxD = VCC TJ,max = 100C CAN bus output recessive CAN bus output dominant VTxD = VCC VTxD = 0 V (Note 15) 2.0 -0.3 -5 -75 - 45 4 65 8 mA mA Pin(s) Parameter Remark / Test Conditions Min Typ Max Unit
TRANSMITTER DATA INPUT High-level input voltage Low-level input voltage High-level input current Low-level input current Input capacitance - - 0 -200 5 VCC + 0.3 +0.8 +5 -350 10 V V mA mA pF
TRANSMITTER MODE SELECT High-level input voltage Low-level input voltage High-level input current Low-level input current Input capacitance Standby mode Normal mode VSTB = VCC VSTB = 0 V (Note 15) 2.0 -0.3 -5 -1 - - - 0 -4 5 VCC + 0.3 +0.8 +5 -10 10 V V mA mA pF
RECEIVER DATA OUTPUT High-level output voltage Low-level output voltage High-level output current Low-level output current Input capacitance IRXD = -10 mA IRXD = 5 mA Vo = 0.7 x VCC Vo = 0.3 x VCC (Note 15) -5 5 - 0.6 x VCC 0.25 -10 10 5 0.75 x VCC 0.45 -15 15 10 V V mA mA pF
15. Characterization Data Only, not tested in production.
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Table 8. DC PARAMETERS CAN TRANSCEIVER
(The DC parameters are given for VCC and temperature in its operating range; TJ = -40 to +150C; RLT = 60 W unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol BUS LINES Vo(reces)
(norm)
Pin(s)
Parameter
Remark / Test Conditions
Min
Typ
Max
Unit
Recessive bus voltage Recessive bus voltage Recessive output current at pin CANH Recessive output current at pin CANL Dominant output voltage at pin CANH Dominant output voltage at pin CANL Differential bus output voltage (VCANH - VCANL) CANH CANL Differential bus output voltage (VCANH - VCANL) Short circuit output current at pin CANH Short circuit output current at pin CANL Differential receiver threshold voltage (see Figure 8) Differential receiver threshold voltage for high common-mode (see Figure 8)) Differential receiver input voltage hysteresis (see Figure 8) Common-mode input resistance at pin CANH Common-mode input resistance at pin CANL Matching between pin CANH and pin CANL common mode input resistance Differential input resistance Input capacitance at pin CANH CANH CANL Input capacitance at pin CANL Differential input capacitance
VTxD = VCC; no load normal mode VTxD = VCC; no load standby mode -35 V < VCANH< +35 V; 0 V < VCC < 5.25 V -35 V 2.0 -100 -2.5 -2.5 3.0 0. 5 1.5 -120 -45 45 0.5 0.40 50 15 15
2.5 0 - - 3.6 1.4 2.25 0 -70 70 0.7 0.7 70 26 26 0 50 7.5 7.5 3.75
3.0 100 +2.5 +2.5 4.25 1.75 3.0 +50 -120 120 0.9 1.00 100 37 37 +3 75 20 20 10
V mV mA mA V V V mV mA mA V V mV kW kW % kW pF pF pF
Vo(reces)
(stby)
Io(reces)
(CANH)
Io(reces)
(CANL)
Vo(dom)
(CANH)
Vo(dom)
(CANL)
Vo(dif) (bus_dom) Vo(dif) (bus_rec) Io(sc) (CANH) Io(sc) (CANL) Vi(dif) (th) Vihcm(dif) (th) Vi(dif) (hys) Ri(cm) (CANH) Ri(cm) (CANL) Ri(cm) (m) Ri(dif) Ci(CANH) Ci(CANL) Ci(dif) VSPLIT VSPLIT
VCANH = VCANL
-3 25
VTxD = VCC; (Note 15) VTxD = VCC; (Note 15) VTxD = VCC; (Note 15) Normal mode; -500 mA < ISPLIT < 500 mA Stand-by mode Normal mode 0.3 x VCC -5 -3
COMMON-MODE STABILIZATION Reference output voltage at pin VSPLIT - 0.7 x VCC +5 +3 mA mA
ISPLIT(i) ISPLIT(lim) PORL
VSPLIT leakage current VSPLIT limitation current POR level
POWER ON RESET (POR) CANH, CANL, Vref in tri-state below POR level 2.2 3.5 4.7 V
15. Characterization Data Only, not tested in production.
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Table 9. AC PARAMETER CAN TRANSCEIVER
The AC parameters are given for VCC and temperature in its operating range; TJ = -40 to +150C; RLT = 60 W unless otherwise specified Symbol Pin(s) Parameter Remark / Test Conditions Min Typ Max Unit
TIMING CHARACTERISTICS td(TxD-BUSon) td(TxD-BUSoff) td(BUSon-RXD) td(BUSoff-RXD) tpd(rec-dom) td(dom-rec) td(stb-nm) tdbus Delay TXD to bus active Delay TXD to bus inactive Delay bus active to RXD Delay bus inactive to RXD Propagation delay TXD to RXD from recessive to dominant Propagation delay TXD to RXD from dominant to recessive Delay standby mode to normal mode Dominant time for wake-up via bus Cl = 100 pF between CANH to CANL Cl = 100 pF between CANH to CANL Crxd = 15 pF Crxd = 15 pF Cl = 100 pF between CANH to CANL Cl = 100 pF between CANH to CANL 40 30 25 40 90 90 5 0.75 7.5 2.5 85 60 55 100 105 105 105 105 230 245 10 5 ns ns ns ns ns ns ms ms
16. Characterization Data Only, not tested in production
+5 V 100 nF
4
VCC
48 52
TxD
CANH 1 nF
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AMIS- 30523
RxD
6 51 49 2
VSPLIT 1 nF CANL
Transient Generator
20 pF
STB
GND
Figure 7. Test Circuit for Transients
VRxD High Low
Hysteresis
0.5
0.9
Vi(dif)(hys)
Figure 8. Hysteresis of the Receiver
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AMIS-30523
+5 V 100 nF
4
VCC
48 52
TxD
CANH RLT VSPLIT 60 W CANL CLT 100 pF
AMIS- 30523
RxD
6 51 49 2
7
20 pF
STB
GND
Figure 9. Test Circuit for Timing Characteristics
TxD 50% 50% VO(dom)CANH VO(reces) VCANL VO(dom)CANL Vi(dif)dom 0.5V td(BUSon-RxD) RxD td(TxD-BUSon) td(rec-dom) 0.3VCC td(dom-rec)
PC20101012.1
VCANH
Vi(dif) = VCANH-VCANL 0.9V
td(TxD-BUSoff) td(BUSoff-RxD) 0.7VCC
Vi(dif)rec
Figure 10. Timing Diagram for AC Characteristics
+5 V 100 nF
4
VCC
48 52
TxD
CANH
6.2 kW 10 nF Active Probe
Generator RxD
6
AMIS-49 30523
7 51 2
CANL 6.2 kW 30 W VSPLIT 30 W 47 nF
Spectrum Anayzer
20 pF
STB
GND
Figure 11. Basic Test Set-up for EME
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AMIS-30523
Figure 12. EME Measurements
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AMIS-30523
TYPICAL APPLICATION SCHEMATIC
100 nF 100 nF
VBB C2 C1
100 mF
100 nF
10 kW
10 kW
C7
R4
C6
100 nF
C5
220 nF
220 nF
R3 VCC POR/WD ERR DO
6 42 18 45 8 9 24 17 10 52 6 51
C4 VCP
22
C3 VBB VBB
1 kW
R2
VDD CPN
46 20
CPP
21
mC
DRIVER diagnostic
25, 26 40, 41 38, 39 34, 35
RESET
MOTXP MOTXN MOTYP MOTYN
M
SPI interface MOTOR positioner CAN controller
DI CLK CS DIR NXT TXD RXD STB
27, 28 31, 32
AMIS-30523
48
CANH
56 W
R5
7
VSPLIT
56 W
C9
D1
3
1
CAN -bus
Table 10. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component C1 C2, C3 C4 C5 C6, C7 C8 C9 R1 R2 R3, R4 R5, R6 D1 17. Low ESR < 1 W. Function VBB buffer capacitor (Note 17) VBB decoupling block capacitor Charge-pump pumping capacitor Charge-pump buffer capacitor VDD buffer capacitor Low pass filter SLA VSPLIT decoupling capacitor Low pass filter SLA Pull up resistor open drain DO output Pull up resistor open drain output CAN termination resistors CAN protection diode Typ Value 100 100 220 220 100 10 47 100 1 10 56 NUP2105 Tolerance -20 +80% -20 +80% $20% $20% $20 % $20% $20% $1% $1% $1% $1% Unit mF nF nF nF nF nF nF W kW kW W
POSITION feedback
R6
49 23 19 1 2 29 30 36 37 43
47 nF 2
CANL
CLR R1
10 nF
SLA GND
TSTO
PC20100126.1
C8
100 W
Figure 13. Typical Application Schematic AMIS-30523
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AMIS-30523
FUNCTIONAL DESCRIPTION MOTOR DRIVER
Introduction
The AMIS-30523 is a micro-stepping stepper motor driver for bipolar stepper motors embedded with an integrated CAN transceiver. The motor driver is connected through I/O pins and a SPI interface with an external microcontroller. It has an on-chip voltage regulator, reset-output and watchdog reset, able to supply peripheral devices. It contains a current-translation table and takes the next micro-step depending on the clock signal on the "NXT" input pin and the status of the "DIR" (=direction) register or input pin. A proprietary PWM algorithm is used for reliable current control. The motor driver provides a so-called "speed and load angle" output. This allows the creation of stall detection algorithms and control loops based on load-angle to adjust torque and speed.
H-Bridge Drivers
The power transistors are equipped with so-called "active diodes": when a current is forced trough the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain-bulk diode of the transistor. Depending on the desired current range and the micro-step position at hand, the RDS(on) of the low-side transistors will be adapted such that excellent current-sense accuracy is maintained. The RDS(on) of the high-side transistors remain unchanged; see Table 5 DC Parameters Motor driver, for more details.
PWM Current Control
A full H-bridge is integrated for each of the two stator windings. Each H-bridge consists of two low-side and two high-side N-type MOSFET switches. Writing logic `0' in bit disables all drivers (high-impedance). Writing logic `1' in this bit enables both bridges and current can flow in the motor stator windings. In order to avoid large currents through the H-bridge switches, it is guaranteed that the top- and bottom-switches of the same half-bridge are never conductive simultaneously (interlock delay). A two-stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly, when excessive voltage is sensed across the transistor, the transistor is switched off. In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope is defined by the gate-drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for slope control (see Table 15 SPI Control Parameter Overview EMC[1:0]).
Icoil Set value
A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the H-bridge switches. The switching points of the PWM duty-cycle are synchronized to the on-chip PWM clock. The frequency of the PWM controller can be doubled and an artificial jitter can be added (see Table 15 SPI Control Parameter Overview PWMJ). The PWM frequency will not vary with changes in the supply voltage. Also variations in motor-speed or load-conditions of the motor have no effect. There are no external components required to adjust the PWM frequency.
Automatic Forward and Slow-Fast Decay
The PWM generation is in steady-state using a combination of forward and slow-decay. The absence of fast-decay in this mode, guarantees the lowest possible current-ripple "by design". For transients to lower current levels, fast-decay is automatically activated to allow high-speed response. The selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation.
Actual value 0 TPWM t
Forward & Slow Decay Fast Decay & Forward
Forward & Slow Decay
Figure 14. Forward and Slow/Fast Decay PWM http://onsemi.com
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AMIS-30523
Automatic Duty Cycle Adaptation
In case the supply voltage is lower than 2 * Bemf, then the duty cycle of the PWM is adapted automatically to >50% to maintain the requested average current in the coils. This
Icoil
Duty Cycle < 50%
process is completely automatic and requires no additional parameters for operation. The over-all current-ripple is divided by two if PWM frequency is doubled (see Table 15 SPI Control Parameter Overview PWMF)
Duty Cycle >50% Actual value
Duty Cycle < 50%
Set value
t TPWM
Step Translator and Step Mode Figure 15. Automatic Duty Cycle Adaption
The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of seven possible stepping modes can be selected through SPI-bits SM[2:0] (see Table 15 SPI Control Parameter Overview ) After power-on or hard reset, the coil-current translator is set to the default 1/32 micro-stepping at position `0'. Upon changing the step mode, the translator jumps to position 0* of the
corresponding stepping mode. When remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. Table 12 lists the output current vs. the translator position. As shown in Figure 16 the output current-pairs can be projected approximately on a circle in the (Ix,Iy) plane. There are, however, two exceptions: uncompensated half step and full step. In these step modes the currents are not regulated to a fraction of Imax but are in all intermediate steps regulated at 100%. In the (Ix,Iy) plane the current-pairs are projected on a square. Table 11 lists the output current vs. the translator position for these cases.
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AMIS-30523
Table 11. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP
Stepmode ( SM[2:0] ) 101 MSP[6:0] 000 0000 001 0000 010 0000 011 0000 100 0000 101 0000 110 0000 111 0000 IY Start = 0 Step 1 Step 2 Step 3 IX Start = 0 Uncompensated Half-Step 0 1 2 3 4 5 6 7 IY Step 1 Start = 0 110 Full Step - 1 - 2 - 3 - 0 IY Step 1 Coil x 0 100 100 100 0 -100 -100 -100 Coil y 100 100 0 -100 -100 -100 0 100 % of Imax
Step 2 I X
IX
Step 3 1/4th Micro Step SM[2:0] = 011 Uncompensated Half Step SM[2:0] = 101
Step 3 Full Step SM[2:0] = 110
Step 2
Figure 16. Translator Table: Circular and Square
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AMIS-30523
Table 12. CIRCULAR TRANSLATOR TABLE
Stepmode (SM[2:0]) 000 MSP[6:0] 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001 001 0010 001 0011 001 0100 001 0101 001 0110 001 0111 001 1000 001 1001 001 1010 001 1011 001 1100 001 1101 001 1110 001 1111 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 1/32 `0' 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 001 1/16 0* - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - 30 - 31 - 010 1/8 0* - - - 1 - - - 2 - - - 3 - - - 4 - - - 5 - - - 6 - - - 7 - - - 8 - - - 9 - - - 10 - - - 11 - - - 12 - - - 13 - - - 14 - - - 15 - - - 011 1/4 0* - - - - - - - 1 - - - - - - - 2 - - - - - - - 3 - - - - - - - 4 - - - - - - - 5 - - - - - - - 6 - - - - - - - 7 - - - - - - - 100 1/2 0* - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - 2 - - - - - - - - - - - - - - - 3 - - - - - - - - - - - - - - - Coil x 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 Coil y 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 0 -3.5 -8.1 -12.7 -17.4 -22.1 -26.7 -31.4 -34.9 -38.3 -43 -46.5 -50 -54.6 -58.1 -61.6 -65.1 -68.6 -72.1 -75.5 -79 -82.6 -84.9 -87.2 -89.5 -91.8 -93 -94.1 -95.3 -96.5 -97.7 -98.8 % of Imax
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AMIS-30523
Table 12. CIRCULAR TRANSLATOR TABLE
Stepmode ( SM[2:0] ) 000 MSP[6:0] 100 0000 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 101 0110 101 0111 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 101 1110 101 1111 110 0000 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 110 1001 110 1010 110 1011 110 1100 110 1101 110 1110 110 1111 111 0000 111 0001 111 0010 111 0011 111 0100 111 0101 111 0110 111 0111 111 1000 111 1001 111 1010 111 1011 111 1100 111 1101 111 1110 111 1111 1/32 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 001 1/16 32 - 33 - 34 - 35 - 36 - 37 - 38 - 39 - 40 - 41 - 42 - 43 - 44 - 45 - 46 - 47 - 48 - 49 - 50 - 51 - 52 - 53 - 54 - 55 - 56 - 57 - 58 - 59 - 60 - 61 - 62 - 63 - 010 1/8 16 - - - 17 - - - 18 - - - 19 - - - 20 - - - 21 - - - 22 - - - 23 - - - 24 - - - 25 - - - 26 - - - 27 - - - 28 - - - 29 - - - 30 - - - 31 - - - 011 1/4 8 - - - - - - - 9 - - - - - - - 10 - - - - - - - 11 - - - - - - - 12 - - - - - - - 13 - - - - - - - 14 - - - - - - - 15 - - - - - - - 100 1/2 4 - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - Coil x 0 -3.5 -8.1 -12.7 -17.4 -22.1 -26.7 -31.4 -34.9 -38.3 -43 -46.5 -50 -54.6 -58.1 -61.6 -65.1 -68.6 -72.1 -75.5 -79 -82.6 -84.9 -87.2 -89.5 -91.8 -93 -94.1 -95.3 -96.5 -97.7 -98.8 -100 -98.8 -97.7 -96.5 -95.3 -94.1 -93 -91.8 -89.5 -87.2 -84.9 -82.6 -79 -75.5 -72.1 -68.6 -65.1 -61.6 -58.1 -54.6 -50 -46.5 -43 -38.3 -34.9 -31.4 -26.7 -22.1 -17.4 -12.7 -8.1 -3.5 Coil y -100 -98.8 -97.7 -96.5 -95.3 -94.1 -93 -91.8 -89.5 -87.2 -84.9 -82.6 -79 -75.5 -72.1 -68.6 -65.1 -61.6 -58.1 -54.6 -50 -46.5 -43 -38.3 -34.9 -31.4 -26.7 -22.1 -17.4 -12.7 -8.1 -3.5 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 % of Imax
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AMIS-30523
Direction Synchronization of Step Mode and NXT Input
The direction of rotation is selected by means of following combination of the DIR input pin and the SPI-controlled direction bit . (see Table 15 SPI Control Parameter Overview)
NXT input
Changes on the NXT input will move the motor current one step up/down in the translator table (even when the motor is disabled). Depending on the NXT-polarity bit (see Table 15 SPI Control Parameter Overview), the next step is initiated either on the rising edge or the falling edge of the NXT input.
Translator Position
The translator position MSP[6:0] can be read in SPI Status Register 3 (See Table 18 SPI Status Registers). This is a 7-bit number equivalent to the 1/32th micro-step from Table 12 "Circular Translator Table". The translator position is updated immediately following a NXT trigger.
When step mode is re-programmed to another resolution (Figure 18), then this is put in effect immediately upon the first arriving "NXT" input. If the micro-stepping resolution is increased, the coil currents will be regulated to the nearest micro-step, according to the fixed grid of the increased resolution. If however the micro-stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro-step translator table. If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro-stepping is proceeds according to the translator table. If the translator position is not shared both by the old and new resolution setting, then the micro-stepping proceeds with an offset relative to the translator table (See Figure 18 right hand side). More information can be found in application note AND8399/D.
NXT
Update Translator Position
Update Translator Position
Figure 17. Translator Position Timing Diagram
Change from lower to higher resolution IY DIR endpos NXT2 NXT3 NXT4 IY NXT1 DIR
Change from higher to lower resolution IY endpos DIR NXT2 IX IY NXT1 startpos DIR
startpos
IX
IX
IX
NXT3
Halfstep
1/4th Step
1/8th Step
Halfstep
Figure 18. NXT-Step-Mode Synchronization
Left: change from lower to higher resolution. The left-hand side depicts the ending half-step position during which a new step mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the micro-step position. Right: change from higher to lower resolution. The left-hand side depicts the ending micro-step position during which a new step mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the half-step position. NOTE: It is advised to reduce the micro-stepping resolution only at micro-step positions that overlap with desired micro-step positions of the new resolution.
Programmable Peak-Current
The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter "CUR[4:0]" (see Table 15 SPI Control Parameter
Overview). Whenever this parameter is changed, the coil-currents will be updated immediately at the next PWM period. Figure 19 presents the Peak-Current and Current Ratings in conjunction to the Current setting CUR[4:0].
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AMIS-30523
Peak Current 1.48 A
Current Range 3 CUR[4:0] = 23 -> 31
630 mA Current Range 2 CUR[4:0] = 16 -> 22 325 mA 166 mA Current Range 0 CUR[4:0] = 0 -> 8 0 8
Current Range 1 CUR[4:0] = 9 -> 15
15
22
31
CUR[4:0]
Figure 19. Programmable Peak-Current Overview Speed and Load Angle Output
The SLA-pin provides an output voltage that indicates the level of the Back-e.m.f. voltage of the motor. This Back-e.m.f. voltage is sampled during every so-called "coil
ICOIL
current zero crossings". Per coil, two zero-current positions exist per electrical period, yielding in total four zero-current observation points per electrical period.
VBEMF t
ZOOM Previous Micro-Step ICOIL Coil Current Zero Crossing Current Decay Zero Current t VCOIL VBB Next Micro-Step
Voltage Transient |VBEMF|
t
Figure 20. Principle of Bemf Measurement
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AMIS-30523
Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. As this transient is not always desired in application software, two operating modes can be selected by means of the bit (see "SLA-transparency" in Table 15 SPI Control Parameter Overview). The SLA pin shows in "transparent mode" full visibility of the voltage transient behavior. This allows a sanity-check of the speed-setting versus motor operation and characteristics and supply voltage levels. If the bit "SLAT" is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA-pin. Because the transient behavior of the coil voltage is not visible anymore, this mode
div2 div4 Ssh Sh buf Csh Ch SLA-Pin
generates smoother Back e.m.f. input for post-processing, e.g. by software. In order to bring the sampled Back e.m.f. to a descent output level (0 to 5 V), the sampled coil voltage VCOIL is divided by 2 or by 4. This divider is set through an SPI bit (see Table 15 SPI Control Parameter Overview). The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil = 0" are internal signals that define together with SLAT the sampling and hold moments of the coil voltage. More information can be found in application note AND8399/D.
VCOIL
Icoil=0 PWMsh
SLAT NOT (Icoil=0)
PWMsh Icoil=0 SLAT VCOIL
t SLA-Pin last sample is retained VBEMF previous output is kept at SLA pin
retain last sample t
SLAT = 1 => SLA-pin is "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated "real-time".
SLAT = 0 => SLA-pin is not "transparent" during VBEMF sampling @ Coil Current Zero Crossing. SLA-pin is updated when leaving current-less state.
Figure 21. Timing Diagram of SLA-Pin Warning, Error Detection and Diagnostics Feedback Thermal Warning and Shutdown Over-Current Detection
When junction temperature rises above TTW, the thermal warning bit is set (Table 17 SPI Status registers Address SR0). If junction temperature increases above thermal shutdown level, then the circuit goes in "Thermal Shutdown" mode () and all driver transistors are disabled (high impedance) (see Table 17 SPI Status registers Address SR2). The conditions to reset flag is to be at a temperature lower than TTW and to clear the flag reading out Status Register 2.
The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current detection threshold, then the over-current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. Each driver transistor has an individual detection bit in (see Table 17 SPI Status registers Address SR1 and SR2: and ). Error condition is latched and the microcontroller needs to clear the status bits (by reading Status Register 1 or 2) to reactivate the drivers.
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AMIS-30523
Note: Successive reading the SPI StatusRegisters 1 and 2 in case of a short circuit condition, may lead to damage to the drivers
Open Coil/Current Not Reached Detection
the required threshold. During that time tCPU will be set to "1".
Error Output
Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle is detected for longer than 200 ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI status register is set ( or ). (Table 17 SPI Status Register Address SR0) When the resistance of a motor coil is very large and the supply voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. Under these conditions the PWM controller duty cycle will be 100% and after 200 ms the error pin and , will flag this situation (motor current is kept alive). This feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil-current or else the coil current should be reduced.
Charge Pump Failure
This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERRB) = OR OR OR < OVCYij> OR OR This open drain output can be wired OR-ed with error outputs other motor drivers.
Logic Supply Regulator
AMIS-30523 has an on-chip 5 V low-drop regulator with external capacitor to supply the digital part of the chip, some low-voltage analog blocks and external circuitry. The voltage level is derived from an internal bandgap reference. To calculate the available drive-current for external circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. See Table 5 DC parameters Motor Driver.
Power-On Reset (POR) Function
The charge pump is an important circuit that guarantees low RDS(on) for all drivers, especially for low supply voltages. If supply voltage is too low or external components are not properly connected to guarantee RDS(on) of the drivers, then the bit is set in Table 17. Also after POR the charge pump voltage will need some time to exceed
The open drain output pin PORB/WD provides an "active low" reset for external purposes. At power-up of AMIS-30523, this pin will be kept low for some time to reset for example an external microcontroller. A small analogue filter avoids resetting due to spikes or noise on the VDD supply.
VBB
t VDD VDDH VDDL < tRF tPU tPD
t
POR/WD pin tPOR tRF
Figure 22. Power-on-Reset Timing Diagram
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AMIS-30523
Watchdog Function
The watchdog function is enabled/disabled through bit (See Table 15 SPI Control Registers address 00h). Once this bit has been set to "1" (watchdog enable), the microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires. In case
VBB
the timer is activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then a reset of the microcontroller will occur through PORB/WD pin. In addition, a warm/cold boot bit is available in Table 17 for further processing when the external microcontroller is alive again. See Figure 23.
t VDD VDDH t tPOR POR/WD pin tDSPI Enable WD > tWDPR and < tWDTO Acknowledge WD t tWDTO = tWDPR or = tWDTO tWDRD tPOR tPU
WD timer
t
Figure 23. Watchdog Timing Diagram
NOTE: tDSPI is the time needed by the external microcontroller to shift-in the bit after a power-up.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See Table 14 SPI Control Registers address 00h). The timing is given in Table 13 below.
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AMIS-30523
Table 13. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]
Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WDT[3:0] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tWDTO (ms) 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512
digital, charge pump remains active. Logic 0 on CLR pin resumes normal operation again. The voltage regulator remains functional during and after the reset and the PORB/WD pin is not activated. Watchdog function is reset completely.
Sleep Mode
CLR Pin (= Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30523, the input CLR needs to be pulled to logic 1 during minimum time given by tCLR. (See Table 6 AC Parameters Motor Driver). This reset function clears all internal registers without the need of a power-cycle, except in sleep mode. The operation of all analog circuits is depending on the reset state of the
The bit in SPI Control Register 2 (See Table 14 SPI Control Registers address 03h) is provided to enter a so-called "sleep mode". This mode allows reduction of current-consumption when the motor is not in operation. The effect of sleep mode is as follows: * The drivers are put in HiZ * All analog circuits are disabled and in low-power mode * All internal registers are maintaining their logic content * NXT and DIR inputs are forbidden * SPI communication remains possible (slight current increase during SPI communication) * Oscillator and digital clocks are silent, except during SPI communication The voltage regulator remains active but with reduced current-output capability (ILOADSLP). The watchdog timer stops running and it's value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. Normal operation is resumed after writing logic `0' to bit . A start-up time is needed for the charge pump to stabilize. After this time, (tcpu) NXT commands can be issued.
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AMIS-30523
SPI INTERFACE The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS-30523. The implemented SPI block is designed to interface directly with numerous micro-controllers from several manufacturers. AMIS-30523 acts always as a Slave and can't initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI).
#CLK Cycle CS 1 2 3 4 5
DO signal is the output from the Slave (AMIS-30523), and DI signal is the output from the Master. A chip select line (CSB) allows individual selection of a Slave SPI device in a multiple-slave system. The CSB line is active low. If AMIS-30523 is not selected, DO is pulled up with the external pull up resistor. Since AMIS-30523 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave.
6 7 8
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
Figure 24. Timing Diagram of a SPI Transfer
NOTE:
At the falling edge of the eighth clock pulse the data-out shift register is updated with the content of the addressed internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS-30523 system clock when CS = High.
Transfer Packet:
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
BYTE 1 Command and SPI Register Address MSB LSB MSB D7 D6 D5 D4 D3 D2 D1 BYTE 2 Data LSB D0
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Command
SPI Register Address
Figure 25. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register Address and indicates to AMIS-30523 the chosen type of operation and addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from AMIS-30523 in a READ operation.
Two command types can be distinguished in the communication between master and AMIS-30523: * READ from SPI Register with address ADDR[4:0]: CMD2 = "0"
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III III IIII IIII
AMIS-30523 * WRITE to SPI Register with address ADDR[4:0]:
CMD2 = "1"
READ Operation
If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the corresponding internal SPI register. In the next 8-bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data.
Registers are updated with the internal status at the rising edge of the internal AMIS-30523 clock when CS = 1 CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO READ DATA from ADDR1 DATA OLD DATA or NOT VALID COMMAND or DUMMY DATA DATA from ADDR1
Figure 26. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
All 4 Status Registers (see Table 17 SPI Registers) contain 7 data bits and a parity check bit The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals "1". If the number of logical ones in D[6:0] is even then the parity bit D7 equals "0". This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. Also the Control Registers can be read out following the same routine. Control Registers don't have a parity check. The CSB line is active low and may remain low between successive READ commands as illustrated in Figure 28. There is however one exception. In case an error condition is latched in one of Status Registers (see Table 17 SPI Registers) the ERRB pin is activated. (See the Error Output section). This signal flags a problem to the external microcontroller. By reading the Status Registers information about the root cause of the problem can be determined. After this READ operation the Status Registers are cleared. Because the Status Registers and ERRB pin (see SPI Registers) are only updated by the internal system clock when the CSB line is high, the Master should force CSB high
immediately after the READ operation. For the same reason it is recommended to keep the CSB line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CSB goes from low to high! AMIS-30523 responds on every incoming byte by shifting out via DO the data stored in the last received address. It is important that the writing action (command - address and data) to the Control Register is exactly 16 bits long. If more or less bits are transmitted the complete transfer packet is ignored (with the exception of preceding read commands (see Figure 28)). A WRITE command executed for a read-only register (e.g. Status Registers) will not affect the addressed register and the device operation. Because after a power-on-reset the initial address is unknown the data shifted out via DO is not valid.
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AMIS-30523
The NEW DATA is written into the corresponding internal register at the rising edge of CS CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO WRITE DATA to ADDR3 DATA NEW DATA for ADDR3
DATA OLD DATA or NOT VALID
DATA OLD DATA from ADDR3
Figure 27. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3 Examples of Combined READ and WRITE Operations
In the following examples successive READ and WRITE operations are combined. In Figure 28 the Master first reads the status from Register at ADDR4 and at ADDR5 followed
Registers are updated with the internal status at the rising edge of the internal 523 clock when CS = 1 CS DI DATA from previous command or NOT VALID after POR or RESET DO COMMAND READ DATA from ADDR4 DATA OLD DATA or NOT VALID COMMAND READ DATA from ADDR5 DATA DATA from ADDR4
by writing a control byte in Control Register at ADDR2. Note that during the write command the old data of the pointed register is returned at the moment the new data is shifted in
The NEW DATA is written into the corresponding internal register at the rising edge of CS COMMAND WRITE DATA to ADDR2 DATA DATA from ADDR5 DATA NEW DATA for ADDR2 DATA OLD DATA from ADDR2
Figure 28. Two Successive READ Commands Followed by a WRITE Command
After the write operation the Master could initiate a read back command in order to verify the data correctly written as illustrated in Figure 29. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is
Registers are Updated with the Internal Status at the Rising Edge of CS CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO WRITE DATA to ADDR2 DATA OLD DATA or NOT VALID DATA
transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CSB line is high, the first read out byte might represent old status information.
Registers are Updated with the Internal Status at the Rising Edge of the Internal 523 Clock when CS = 1
COMMAND READ DATA from ADDR2 DATA OLD DATA from ADDR2 COMMAND or DUMMY DATA NEW DATA from ADDR2
NEW DATA for ADDR2 DATA OLD DATA from ADDR2
Figure 29. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by a READ Back Operation to Verify a Correct WRITE Operation
NOTE: The internal data-out shift buffer of the AMIS-30523 is updated with the content of the selected SPI register only at the last (every eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
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AMIS-30523
Table 14. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to "0" after power-on or
hard reset.) Structure Content Access Address WR (00h) CR0 (01h) CR1 (02h) CR2 (03h) Reset Data Data Data Data DIRCTRL MOTEN Bit 7 R/W 0 WDEN SM[2:0] NXTP SLP - SLAG - SLAT PWMF - Bit 6 R/W 0 Bit 5 R/W 0 WDT[3:0] Bit 4 R/W 0 Bit 3 R/W 0 Bit 2 R/W 0 - CUR[4:0] PWMJ - - EMC[1:0] - Bit 1 R/W 0 - Bit 0 R/W 0 -
Where: R/W Reset:
Read and Write access Status after power-On or hard reset
Table 15. SPI CONTROL PARAMETER OVERVIEW
Symbol Description = 0 DIRCTRL Controls the direction of rotation (in combination with logic level on input DIR) = 1 = 0 = 1 00 EMC[1:0] Turn On - Turn-off Slopes of motor driver (Note 18) 01 10 11 SLAT SLAG PWMF PWMJ Speed load angle transparency bit Speed load angle gain setting Enables doubling of the PWM frequency (Note 18) Enables jittery PWM = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 000 001 010 SM[2:0] Stepmode 011 100 101 110 111 SLP MOTEN Enables sleep mode Activates the motor driver outputs = 0 = 1 = 0 = 1 Status = 0 = 1 = 0 = 1 NXTP Selects if NXT triggers on rising or falling edge Value CW motion CCW motion CCW motion CW motion
Trigger on rising edge Trigger on falling edge Very Fast Fast Slow Very Slow SLA is transparent SLA is NOT transparent Gain = 0.5 Gain = 0.25 Default Frequency Double Frequency Jitter disabled Jitter enabled 1/32 Micro - Step 1/16 Micro - Step 1/8 Micro - Step 1/4 Micro - Step Compensated Half Step Uncompensated Half Step Full Step n.a. Active mode Sleep mode Drivers disabled Drivers enabled
18. The typical values can be found in Table 5: DC Parameters Motor Driver and in Table 6: AC parameters Motor Driver
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AMIS-30523
CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
Table 16. SPI CONTROL PARAMETER OVERVIEW CUR[4:0]
Current Range (Note 20) Index CUR[4:0] 0 00000 1 00001 2 00010 3 00011 0 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 1 12 01100 13 01101 14 01110 15 01111 Current (mA) (Note 19) 33 64 95 104 115 126 138 153 166 190 205 230 250 275 300 325 3 2 Current Range (Note 20) Index CUR[4:0] 16 10000 17 10001 18 10010 19 10011 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 26 11010 27 11011 28 11100 29 11101 30 11110 31 11111 Current (mA) (Note 19) 365 400 440 485 530 585 630 750 825 895 975 1065 1155 1245 1365 1480
19. Typical current amplitude at TJ = 125C 20. Reducing the current over different current ranges might trigger overcurrent detection. See application note AND8372/D for solutions.
SPI Status Register Description
All 4 SPI status registers have Read Access and are default to "0" after power-on or hard reset.
Table 17. SPI STATUS REGISTERS
Structure Content Access Address SR0 (04h) SR1 (05h) SR2 (06h) SR3 (07h) Reset Data is not latched Data is latched Data is latched Data is not latched Bit 7 R 0 PAR PAR PAR PAR Bit 6 R 0 TW OVCXPT OVCYPT Bit 5 R 0 CPfail OVCXPB OVCYPB Bit 4 R 0 WD OVCXNT OVCYYNT Bit 3 R 0 OPENX OVCXNB OVCYNB MSP[6:0] Bit 2 R 0 OPENY - TSD Bit 1 R 0 - - - Bit 0 R 0 - - -
Where: R Reset PAR
Read only mode access Status after power-on or hard reset Parity check
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AMIS-30523
Table 18. SPI STATUS FLAGS OVERVIEW
Mnemonic CPFail Flag Charge pump failure Length (bit) 1 Related SPI Register Status Register 0 Comment `0' = no failure `1' = failure: indicates that the charge pump does not reach the required voltage level. Translator micro step position `1' = Open coil detected `1' = Open coil detected `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor XN-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor XN-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor XP-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor XP-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor YN-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor YN-terminal `0' = no failure `1' = failure: indicates that over current is detected at bottom transistor YP-terminal `0' = no failure `1' = failure: indicates that over current is detected at top transistor YP-terminal Reset State `0'
MSP[6:0] OPENX OPENY OVCXNB
Micro-step position OPEN Coil X OPEN Coil Y OVer Current on X H-bridge; MOTXN terminal; Bottom tran. OVer Current on X H-bridge; MOTXN terminal; Top transist. OVer Current on X H-bridge; MOTXP terminal; Bottom transist. OVer Current on X H-bridge; MOTXP terminal; Top transist. OVer Current on Y H-bridge; MOTYN terminal; Bottom transist. OVer Current on Y H-bridge; MOTYN terminal; Top transist. OVer Current on Y H-bridge; MOTYP terminal; Bottom transist. OVer Current on Y H-bridge; MOTYP terminal; Top transist. Thermal shutdown Thermal warning Watchdog event (Note 21)
7 1 1 1
Status Register 3 Status Register 0 Status Register 0 Status Register 1
`0000000' `0' `0' `0'
OVCXNT
1
Status Register 1
`0'
OVCXPB
1
Status Register 1
`0'
OVCXPT
1
Status Register 1
`0'
OVCYNB
1
Status Register 2
`0'
OVCYNT
1
Status Register 2
`0'
OVCYPB
1
Status Register 2
`0'
OVCYPT
1
Status Register 2
`0'
TSD TW WD
1 1 1
Status Register 2 Status Register 0 Status Register 0 `1' = watchdog reset after time-out
`0' `0' `0'
21. WD - This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to "1" after reset, it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master writes "0" to WDEN bit.
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AMIS-30523
FUNCTIONAL DESCRIPTION CAN TRANSCEIVER
Introduction
The CAN transceiver is the interface between a (CAN) protocol controller and the physical bus. It provides differential transmit capability to the bus and differential receive capability to the CAN controller. Due to the wide common-mode voltage range of the receiver inputs, it is able to reach outstanding levels of electro-magnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. Additional features are the ideal passive behavior when the supply voltage is removed; a wake-up over bus and the extreme low current in stand-by mode. To cope with the long bus delay the communication speed needs to be low. The integrated transceiver allows low transmit data rates down 10 kbit/s or lower.
Operating Modes
a time period of tBUS, the RxD pin is driven low by the transceiver to inform the controller of the wake-up request.
Split Circuit
The VSPLIT pin is operational only in normal mode. In standby mode this pin is floating. The VSPLIT is connected as shown in Figure 13 and its purpose is to provide a stabilized DC voltage of 0.5 x VCC to the bus avoiding possible steps in the common-mode signal therefore reducing EME. These unwanted steps could be caused by an un-powered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 x VCC voltage.
Wake-up
Once a valid wake-up (dominant state longer than tBUS) has been received during the standby mode the RxD pin is driven low
Over-Temperature Detection
The CAN transceiver provides two modes of operation as illustrated in Table 19. These modes are selectable through pin STB
Table 19. OPERATING MODES
RXD Mode Normal Standby STB Low High Low Bus dominant Wake-up request detected High Bus recessive No wake-up request detected
A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 160C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off-state resets when pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits.
High Communication Speed Range
In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME. In stand-by mode both the transmitter and receiver are disabled and a very low-power differential receiver monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 mA. When a wake-up request is detected by the low-power differential receiver, the signal is first filtered and then verified as a valid wake signal after
The transceiver is primarily intended for industrial applications. It allows very low baud rates needed for long bus length applications. But also high speed communication is possible up to 1 Mbit/s.
Fail Safe Features
A current-limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 7). Pins TxD and STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed.
DEVICE ORDERING INFORMATION
Part Number AMIS30523C5231RG AMIS30523C5231G Temperature Range -40C - 125C -40C - 125C Peak Current 1600 mA 1600 mA Package Type QFN-52 (Pb-Free) QFN-52 (Pb-Free) Shipping Tape & Reel Tube
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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AMIS-30523
PACKAGE DIMENSIONS
QFN52 8x8, 0.5P CASE 485M-01 ISSUE C
D A B
PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A2 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50
2X
0.15 C
2X
0.15 C A2 0.10 C A 0.08 C
SEATING PLANE
A1 D2
14
52 X
L
13
1 52 X
K
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEEE EEEE EEEE EEEE
A3
REF 26 27
E
RECOMMENDED SOLDERING FOOTPRINT
C 8.30 6.75 0.62
52X
E2
6.75
8.30
39 52 40 PKG OUTLINE
e
52 X
b
NOTE 3
0.50 PITCH
0.30
DIMENSIONS: MILLIMETERS
52X
0.10 C A B 0.05 C
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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pubnumber/D

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